Computer and Modernization ›› 2013, Vol. 1 ›› Issue (9): 190-194,.doi: 10.3969/j.issn.1006-2475.2013.09.047

• 应用与开发 • Previous Articles     Next Articles

Parameter Optimization of High-reliable Bus in System-on-Chip

YE Ning1, YING Ren-dong1, ZHU Xin-zhong2, LI Chao2, LIU Pei-lin1   

  1. 1. Shanghai Key Laboratory of Navigation and Location Based Service, Shanghai Jiaotong University, Shanghai 200240, China;2. Shanghai Spaceflight Computer Technology Institute, Shanghai 200050, China
  • Received:2013-05-02 Revised:1900-01-01 Online:2013-09-17 Published:2013-09-17

Abstract: In order to enhance the robustness of SoC against single event effect (SEE), we focused on the improving of reliability for bus on chip. We built models for error rate of bus and equations of bus reliability. Concerning three situations, we restricted the value of parameters and thus, discussed the optimization of the parameters. For each of the situation, we give the optimized value of parameters that brings us the highest reliability for bus on chip.

Key words: single event effect, reliability, modeling, parameter optimization

CLC Number: